The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a FinFET anti-fuse structure that contains multiple breakdown points and a method of forming the same.
An anti-fuse is an electrical device that performs the opposite function to a fuse. Whereas a fuse starts with a low resistance and is designed to permanently break an electrically conductive path (typically when the current through the path exceeds a specified limit), an anti-fuse starts with a high resistance and is designed to permanently create an electrically conductive path (typically when the voltage across the anti-fuse exceeds a certain level).
Programmable on-chip anti-fuses are needed in many circuit applications. In some applications, it preferable to fabricate on-chip anti-fuses during FinFET CMOS fabrication in order to minimize process cost and improve system integration. The breakdown voltage of conventional planar anti-fuses with a gate dielectric is too high. Also, planar anti-fuses use too much area compatible with current ground rules of 14 nm, 10 nm or 7 nm technology. Therefore, there is a need for improved on-chip FinFET compatible anti-fuses.